Priority is claimed to Japanese Patent Application Number JP2006-119651 filed on Apr. 24, 2006, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device in which ESD (Electro-Static Discharge) resistance is improved, and a method of manufacturing the same.
2. Description of the Related Art
As an example of conventional semiconductor devices, the following device using surge protection elements has been known. For example, a total of four surge protection elements are disposed respectively near four sides of a rectangular or substantially rectangular pad, one on each side. The pad is connected with one of electrodes of each of the surge protection elements by wiring. A wire for distributing a surge current is connected with the other one of the electrodes of each of the surge protection elements by wiring. Note that a potential of the pad is supplied to an internal circuit through the wiring. Moreover, each of the surge protection elements is, for example, a Zener diode, a PMOS diode or an NMOS diode. By use of this structure, the surge current applied to the pad is dispersed to all of the surge protection elements disposed around the pad. Accordingly, a surge breakdown resistance of a semiconductor device is improved. This technique is described for instance in Japanese Patent Application Publication No. 2002-313947.
As another example of conventional semiconductor devices, the following insulated gate bipolar transistor including surge protection elements has been known. For example, an N type epitaxial layer used as a drift layer is formed on a P type semiconductor substrate used as a collector layer. In an N type epitaxial layer used as an internal cell part, P type diffusion layers used as channel regions are formed. Moreover, in each of the P type diffusion layers, N type diffusion layers used as emitter regions are formed. Furthermore, in an N type epitaxial layer used as an electrode pad or a field plate part, a P type diffusion layer having the same shape as that of the P type diffusion layer used as the channel region is formed. By use of this structure, when ESD surge is applied to a collector electrode, avalanche breakdown occurs evenly in the entirety of a chip. Accordingly, current concentration in a certain region is prevented. As a result, surge resistance of the entirety of the chip to ESD is improved. This technique is described for instance in Japanese Patent Application Publication No. 2003-188381.
As described above, a structure for the conventional semiconductor device has been known, in which a plurality of surge protection elements are disposed around a pad, and in which a surge current applied to the pad is dispersed to all of the surge protection elements. By using this structure, the surge current is prevented from flowing into an internal circuit, and is thereby prevented from breaking down the internal circuit. However, the following problem may occur depending on the magnitude of the surge current and the like. Specifically, a problem of breakdown of an internal circuit may occur, when the surge current is too large, for example. This is because the surge protection elements around the pad cannot cope with such a large surge current into the internal circuit.
Moreover, as described above, a structure for the conventional semiconductor device has been known, in which avalanche breakdown occurs evenly in the entirety of a chip when ESD surge is applied to a collector electrode. In this structure, the avalanche breakdown also occurs in an internal cell when the ESD surge is applied. Accordingly, depending on the magnitude of the applied ESD surge, a problem may occur that the internal cell is broken down.